The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Referring now to FIG. 1, a functional schematic of a memory structure is presented. A row decoder 102 activates one or more word lines 104. Values are read from or written to memory cells 106 of the selected word line 104 via bit lines 108. The memory cells 106 each include a transistor 110 and a capacitor 112. For example only, the transistor 110 may be a metal-oxide-semiconductor field-effect transistor (MOSFET) having a gate, a source, and a drain.
For example only, the transistor 110 may be an n-channel MOSFET. The drain of the transistor 110 is connected to the respective bit line 108 and the gate of the transistor 110 is connected to the respective word line 104. The source of the transistor 110 is connected to a first terminal of the capacitor 112. A second terminal of the capacitor 112 is connected to a ground potential.